1. Field of the Invention
The present invention generally relates to dynamic random access memories (DRAMs), embedded DRAMs and computer memory systems and, more particularly, to DRAMs where high-speed synchronous data transfer is required.
2. Background Description
Recently, many kinds of high-speed DRAMs, such as synchronous DRAM (SDRAM), are being used in computer systems. This is because the rapid increase in central processor unit (CPU) performance (about 70% annually) requires much faster instruction and data streams transferred between the CPU and DRAMs, while the access time for the conventional fast page mode DRAMs has not been improved much. However, an ever increasing number of new kinds of DRAMs require enormous design effort since, for example, existing SDRAMs require a totally new design almost from scratch in order to achieve high data rates. In addition, various application needs, such as a wide input/output (I/O) data path, increase the design effort even more. Another problem related to existing SDRAMs is that the clock distribution over the chip in SDRAMs is a considerable source of power consumption. Moreover, existing SDRAMs exhibit very slow performance if the clock frequency is low. This situation often occurs in low-end embedded applications.
FIGS. 1A and 1B show timing diagrams for existing asynchronous and synchronous DRAM interfaces, respectively, in 4-bit burst read operations. In an asynchronous interface, the high-to-low transitions of the RAS (row address strobe) and CAS (column address strobe) signals, respectively latch the multiplexed row and column addresses and start the row and column access operations. The CAS operations need to be repeated four times to get four bits of data out. The low-to-high transitions start pre-charging operations of the row and column circuitry. On the other hand, the SDRAM, which is disclosed in U.S. Pat. No. 5,404,338 operates in synchronization with clock signals to function as a main storage for high speed CPUs and graphics accelerators.
FIG. 1B shows typical access cycles in the SDRAM in the JEDEC (Joint Electron Device Engineering Council) standard synchronous interface. The row and column address strobes and accesses start by setting the RAS and CAS signals to low at the rising edge of the clock, occur in clocks numbers 1 and 3, respectively. In the 4-bit burst mode operations, the succeeding column addresses are generated internally in linear or interleaved manner. The data output starts after a pre-determined clock cycle (in this case in clock number 5). Precharging the row circuitry starts in clock number 7 when the RAS signal is set to low after the column burst operations finish, while the CAS does not need a pre-charge operation. The RAS and CAS access latencies are limited only a few selections which are defined in the mode register as the integer multiple of the clock cycles. Here, latency means the number of clock cycles from starting the access to the acquisition of the data. This limitation results in narrow coverage of the clock frequencies of the SDRAM. In other words, if the frequency is too high, the memory access operations cannot catch-up to the clock, while if the clock frequency is too low, the memory access operations take much longer time than the DRAM really can provide.
FIG. 2 shows a typical block diagram of existing SDRAM design using a full custom approach down to the transistor level. The memory arrays 1a and 1b are configured in a two-bank architecture. By interleaving the memory access to the two banks, the access latency due to the pre-charge operations of the row circuitry can be minimized. Outputs from the memory arrays 1a and 1b are respectively provided to sense amplifiers 2a and 2b. The memory arrays 1a and 1b are addressed by row decoders 7a and 7b and column decoders 3a and 3b, respectively. The various control circuits, such as sequential control 5a and 5b and row column select 6a and 6b, are supplied with inputs from command decoder 102. Inputs to the command decoder are provided by the write enable (WE) buffer 104, the CAS buffer 105, the RAS buffer 106, and the chip select (CS) buffer 107.
The circuitry on the SDRAM chip is synchronous with a clock (CLK) from clock buffer 109 synchronized by an external clock (CKE) supplied by buffer 110. The clock lines, drawn by thick solid lines, reaches all across the chip, resulting in the larger power consumption for the clock related circuits. This is particularly serious if the pipeline architecture is used for the column circuitry for improved data rate.
Secondly, a high performance synchronous memory system is disclosed in, for example, U.S. Pat. No. 5,291,580, consists of the standard DRAMs, latch and buffer circuits and control circuits implemented in separate chips. However, the system is not designed for a memory system that is logically and physically compatible with existing SDRAM and SDRAM SIMM (single in-line memory module).
Finally, a synchronous DRAM memory module is disclosed in U.S. Pat. No. 5,494,435. However, it is rather a straight forward implementation using synchronous DRAMs with better placement of the clock driver for higher clock rate.